The emergence and development of sub 100 nm complementary metal-oxide semiconductor (CMOS) technology and the availability of high-speed metal-oxide semiconductor field-effect transistors (MOSFETs) in low cost silicon processes has resulted in the proliferation of CMOS technology for radio-frequency (RF) and wireless applications. With an ever increasing demand for higher data bandwidth, system performance and lower spectral occupancy and pressure to reduce overall system cost and form factors, CMOS wireless applications continue to move to increasingly higher RF frequencies, and well into the mm-wave regime.
Many applications, such as automotive radar and wireless communication systems such as WiMax, can greatly benefit and may utilizes ever faster silicon processes. Devices fabricated using CMOS processes, however, have inherently relatively lower output power. As the frequency increases, extracting the RF and mm-wave power from the integrated circuits (IC) becomes increasingly more challenging. The loss in the printed circuit board (PCB) substrates as well as the difficulty in modeling the exact interface of the CMOS IC and PCB has hindered the rate of progress.
On-chip antennas have been proposed to utilize the relatively inexpensive and reliable CMOS process to combat this difficulty and reduce the cost of fabrication of high frequency components required for mm-wave links. The main challenge in CMOS radiators is the loss associated with such radiators.